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DescriptionThe PRL-4220 is a 2 x 1:10 fanout 50 Ω TTL Line Driver. It is intended for distribution of two independent high-speed clock and logic signals (e.g. CLK and DATA) to multiple loads via long lines. The 50 Ω back-terminated outputs can drive long lines with or without 50 Ω load terminations. With 50 Ω load terminations, however, all outputs of the PRL-4220 can drive 100 ft of 50 Ω cables at clock rates greater than 80 MHz. The PRL-4220 is implemented as two separate, independent 1:10 fanout buffers on two PCBs in a single enclosure. The input resistance of each 1:10 fanout board can be independently selected to be either 50 Ω or 10 kΩ by a switch. The 10 kΩ-input is desirable when interfacing with low power circuits. The 50 Ω back terminated outputs typically deliver 2.5 V into 50 Ω or 5.0 V into Hi-Z loads. All I/Os are DC coupled and have BNC or SMA connectors. Each board also has a TTL-compatible EN input pulled down via a 1 kΩ resistor. When left open the Enable is active, and the fanout buffer will output signals. Each board can be disabled by driving its EN input high. The PRL-4220 is housed in a 3.0 x 6.8 x 4.0-in. extruded aluminum enclosure and is supplied with the PRL-760E, ±9.0 V/±1.8 A AC/DC Adapter. A block diagram showing the equivalent input and output circuits of the PRL-4220 is shown in Fig. 1. Related Products: |
(0° C ≤ TA ≤ 35° C)*
| Symbol | Parameter | Min | Typ | Max | Unit | Comments |
|---|---|---|---|---|---|---|
| RIN Low | Input Resistance Low Range | 49.5 | 50.0 | 50.5 | Ω | |
| RIN Hi | Input Resistance High Range | 9.9 | 10.0 | 10.1 | kΩ | |
| RIN EN | Input Resistance, Enable | 1 | kΩ | |||
| ROUT | Output Resistance | 50 | Ω | |||
| VIL | TTL Input Low Level | -0.5 | 0.0 | 0.5 | V | |
| VIH | TTL Input High Level | 2.0 | 2.4 | 5.0 | V | |
| VIL EN | EN Input Low Level | -0.5 | 0.0 | 0.5 | V | |
| VIH EN | EN Input High Level | 2.0 | 2.4 | 5.0 | V | Drive EN High to disable output |
| VOL | TTL Output Low Level | 0.0 | 0.25 | 0.5 | V | RL=50 Ω |
| VOH1 | TTL Output High Level | 2.2 | 2.5 | V | RL=50 Ω @ DC | |
| VOH2 | TTL Output High Level | 4.4 | 5.0 | V | RL=1 MΩ @ DC | |
| IDC1 | DC Input Current | 1000 | mA | F =50 MHz sq. wave(1) | ||
| IDC2 | DC Input Current | 1230 | mA | F ≤ 100 MHz | ||
| IDC3 | DC Input Current | 1450 | mA | F =125 MHz | ||
| VDC | DC Input Voltages | 7.75 | 8.50 | 12.00 | V | |
| VAC | AC/DC Adaptor Input Voltage | 103 | 115 | 127 | V | |
| TPLH | Propagation Delay to output ↑ | 9 | 12 | ns | ||
| TPHL | Propagation Delay to output ↓ | 9 | 12 | ns | ||
| tr | Rise Time (10%-90%) | 1.8 | 2.5 | ns | ||
| tf | Fall Time (10%-90%) | 1.5 | 2.5 | ns | ||
| TSKEW1 | Skew between any 2 outputs | 500 | 900 | ps | Within one 1:10 bank | |
| TSKEW2 | Skew between any 2 outputs | 1000 | 1400 | ps | Any two outputs | |
| FMAX1 | Max. Clock Frequency(2) | 100 | 125 | MHz | RG58C/U, cable length =3 ft | |
| FMAX2 | Max. Clock Frequency(3) | 80 | RG58C/U, cable length = 100 ft | |||
| PWMIN1 | Minimum Pulse Width | 4 | ns | ↑ Input | ||
| PWMIN2 | Minimum Pulse Width | 6 | ns | ↓ Input | ||
| Size | 3.0 x 6.8 x 4.0 | in | ||||
| Weight | 1.5 | lb | Excluding AC adapter | |||
| Shipping Weight | 1.5 | lb | Including AC adapter | |||
Notes:
- fMAX should not exceed 125 MHz, otherwise damage of the unit due to overheating may result.
- fMAX2 is measured by driving a second PRL-4110 at the end of a 100 ft cable.
- For sharing a single PRL-760E, ±9.0 V, ±1.8 A AC/DC adapter, the total current should not exceed 1.8 A.
