The PRL-425QLT is a four channel LVDS receiver with single-ended 50 Ω TTL output line drivers. It is intended for converting differential signals transmitted through long lines into single-ended TTL outputs. The floating 100 Ω inputs are designed to be compatible with LVDS or source-biased LVPECL differential input signals. The 50 Ω back-terminated TTL output line drivers can drive long lines with or without terminations, and they are designed specifically for use with high speed data communication applications. Fig. 1 shows the standard LVDS input configuration. Functional block diagrams are shown in Figs. 2-3.
A feature of the TI DS90LV12A receiver chip in the PRL-425QLT is a “fail safe” state that sets the output logic Hi (TTL True) if the inputs are at the same voltage, which occurs if the inputs are left to float open or if they are shorted to GND. If this is undesired in your application, please consider the PRL-425T, 2 Ch. Universal Differential Receiver with TTL Outputs.
Each PRL-425QLT is supplied with a ±8.5 V/1.8 A AC/DC Adapter, but it can also operate from a single positive power supply in the range of +7.5 V to +12 V. The PRL-425QLT-SMA has SMA I/Os and is housed in a 1.3 x 2.9 x 2.9-in. extruded aluminum enclosure, while the PRL-425QLT-RJRJ has RJ45 I/Os and a length of 3.9-in.
The PRL-425QLT-RJRJ allows the replacement of up to 12 coax cables by 2 double-shielded Cat7/Cat8 network cables to reduce cabling and complexity in high-density applications. While Cat7/Cat8 cabling was designed to carry differential signaling, such as LVDS, the shielded twisted pairs have a single-ended impedance of ~54 Ohms when one wire is grounded, and they can carry single-ended TTL signals at up to 100 MHz, as shown in our impedance study.
A future version, PRL-425QLT-RJS, with an RJ45 input and SMA outputs, is planned, but with no guarantee of an availability date.
Available accessories include TTL Fanout modules, voltage distribution modules, brackets for mounting multiple units, and a rackmount enclosure kit for rapid system integration.
SPECIFICATIONS (0° C ≤ TA ≤ 35° C)*
|RIND||Differential Input Resistance||100||Ω|
|RINC||Common Mode Input Resistance||5K||Ω|
|IDC1||DC Input Current @ 50 MHz||265||280||mA|
|IDC2||DC Input Current @ 85 MHz||340||360||mA|
|VIA||Single ended input(1)||-0.3||3.9||V|
|VCM||Common Mode Input(1)||0||3||V|
|VDC||DC Input Voltage||7.5||8.5||12.0||V|
|VAC||AC/DC Adapter Input Voltage||103||115||127||V|
|VOHNL||Output Hi Level, No Load||4.4||5.0||V||RL=1 MΩ @ DC|
|VOHFL||Output Hi Level, Full load||2.2||2.5||V||RL=50 Ω @ DC|
|VOLNL||Output Lo Level, No Load||-0.1||0.0||0.4||V||RL=1 MΩ @ DC|
|VOLFL||Output Lo Level, Full Load||-0.05||0.00||0.20||V||RL=50 Ω @ DC|
|TPLH||Propagation Delay to output ↑||2.2||ns|
|TPHL||Propagation Delay to output ↓||2.2||ns|
|tr||Rise Time (10%-90%)||1.8||2.5||ns||PRL-425QLT-SMA|
|tf||Fall Time (10%-90%)||1.8||2.5||ns||PRL-425QLT-SMA|
|TSKEW||Skew between any 2 outputs||250||600||ps|
|FMAX1||Max. Clock Frequency(2)||90||100||MHz||PRL-425QLT-SMA|
|DTY||Positive Duty Cycle @ 50 MHz||55||%||↑ Input|
|Size||1.3 x 2.9 x 2.9||in||PRL-425QLT-SMA|
|Size||1.3 x 2.9 x 2.9||in||PRL-425QLT-RJRJ|
|Weight, excluding AC adapter||5||Oz|
|Shipping weight, Including AC adapter||4||lb|
(1): See Fig. 1