2 Channel Differential Pickoff Tee


$ 402.50


  • In-Line GHz ECL and RF Signal Monitoring
  • Differential Signal Monitoring
  • Permanent In-line Installations for System Monitoring
  • Trigger Pick-Off Signal Generation


  • Dual Channel for CLK/DATA Monitoring
  • SMA I/O, 50 Ω Impedance
  • Through Port Bandwidth > 7 GHz
  • Monitor Port Bandwidth > 6 GHz
  • Through Port Retains 95% of Input Signal (0.42 dB insertion loss)
  • Monitor Port Retains 10% of Through Signal (20 dB attenuation ratio)
  • Applicable to Single-Ended or Differential Inputs


The PRL-860D is a series of dual channel wideband signal splitters, intended for inline signal monitoring applications. As shown below, the input signal travels from Input Port D to the Through Port QT via a 50 Ω transmission line. A small fraction of the input signal is extracted by the 450 Ω resistor and diverted to the Monitor Port QM. A typical connection set up is shown in Fig. 1. The signal generator with a source resistance RS is connected to Port D, and QT is connected to the intended load RL. QM, which monitors the input signal going through QT, is connected to a 50 Ω input scope.

When operating in a 50 Ω environment, typically 95% of the input signal applied to port D is transmitted to port QT and 10% to port QM. For optimum inline monitoring performance, QM must always be connected a 50 Ω-input instrument. QT, however, can be left open or connected to an arbitrary load, because it is the function of the QM port to capture the input signal when it is going through the QT port. For example, if QT is left open, QM will display the input signal at the end of a transmission line terminated into 500 Ω. More detailed discussion on this subject will be made available on our website.

From Fig. 1, before QM is connected to the scope, the Thevenin output impedance ZTH looking into the 50 Ω Z0 bus is simply RS//RL, and the Thevenin output voltage measured at the same point is VTH. After QM is connected to the scope, the equivalent circuit is shown in Fig. 2, where ZTH and VTH are given in Fig.1. Fig. 2 is intended for DC calculations only, as it does not include the interconnecting cable between QT and the load RL. For a given input VS, the Through port voltage VQT and the Monitor Port voltage VQM can be calculated as follows:

Fig. 1. Typical Set Up

Fig. 2. Simplified Equivalent Circuit of Fig. 1

  1. From Fig. 2, VQT = VTH x 500/( ZTH + 500)
    If RS = RL = 50 Ω, then,
    ZTH = 25 Ω, and VTH = VS/2, or 0.5 VS.
    Using these values of ZTH and VTH in (1)
  2. VQT =0.476 VS

Equation (2) states that, after loading the QM port, the Through Port output is reduced to 0.476/0.5 = 95.2% of VTH, the unloaded value. From Fig. 2, VQM is simply 0.1 VQT, due to the 450 Ω/50 Ω, 10 to 1 divider.

Related models:

  • PRL-860Q-SMA, 4 SMA Inputs, 4 SMA Through Ports, 4 SMA Monitor Ports, for simultaneous CLK/Data monitoring. This unit comprises two identical PCBs in one enclosure, and therefore is functionally equivalent to two units of PRL-860D-SMA.
  • PRL-860Q-TR, 2 Triax Inputs, 2 Triax Through Ports, 4 SMA Monitor Ports, for simultaneous CLK/Data monitoring, coming soon.

Additional models with different attenuation options will be available by special order.

Fig. 1, PRL-860D-SMA Block Diagram
Fig. 2, PRL-860D-TR Block Diagram

Bandwidth and Rise Time Considerations for Ideal Passive Loading Conditions

From Fig. 1, it is seen that the path from the input connector D to the Through Port connector QT is simply a very short 50 Ω transmission line shunted by a 500 Ω load. The bandwidth is limited by the PCB material and the microstrip line Z0 on the PCB surface. When driven by the Tektronix 80E04 TDR generator (tR = 25 ps) the Through Port QT1, Fig. 3 C3, shows a rise time of 52 ps. With the source rise time of 25 ps taken into account, the rise time of QT1 is actually less than 46 ps, or an equivalent BW greater than 7.6 GHz. The Monitor Port, QM1, Fig. 3, C4, shows a slower rise time of 59 ps, or an equivalent BW greater than 6 GHz.

The slight overshoot and the perturbations on the pulse top shown in Fig 3, C4, are due to the capacitive coupling effect across the 450 Ω resistor. When a slower rise time input signal of 150 ps is used, both the overshoot and pulse top perturbations are greatly reduced, as shown in Fig. 4, C4. It should be noted that the set up used in both Fig. 3 and Fig. 4 is based on that shown in Fig. 1, and both QT and QM outputs are connected to sampling scope inputs, which are essentially ideal 50 Ω terminations. When real life receivers are involved, as will be shown in a separate Application Note, signal kickback will occur when the receivers are switched on and off. These kickback signals, visible only through the QM port, are seldom of concern until things are not working correctly.

Fig. 3: C3/QT1 and C4/QM1 driven by Tek 80E04 TDR (tR = 25 ps)

Fig. 4. C3/QT2 and C4/QM2 driven by PRL-430LP (tR = 150 ps)

These test results, though typical, are not guaranteed performance specifications.

(0° C ≤ TA ≤ 35° C)*

Min Typ Max
RIN Input Resistance (VIN port D) 45.00 45.45 45.90 Ω
ROUT I Output Resistance (QT port) 45.00 45.45 45.90 Ω
ROUT II Output Resistance (QM port) 470 475 480 Ω
tR1(1) QT Rise Time (10%-90%)   50 60 ps
BW1 Equivalent 3 dB Bandwidth 5.8 7.0   GHz
tR2(1) QM Rise Time (10%-90%)   55 65 ps
BW2 Equivalent 3 dB Bandwidth 5.3 6.0   GHz
tPLHI Propagation Delay to QT Port   300   ns
tPLHII Propagation Delay to QM Port   350   ns
ILPCT Insertion Loss, QT Port, %   5   %
ILdB Insertion Loss, QT Port, dB   0.42   dB
tSKEW Skew between QT and QM   75 150 ps
  Size 2.9W x 1.3H x 1.5L in.
  Weight 5 Oz
Specifications for Triax model PRL-860D-TR coming soon.
* All measurements are made with outputs terminated into 50 Ω.
(1) The output rise and fall times are measured with with all inputs terminated into 50 Ω.