The PRL-450LPD logic translator converts LVPECL signals to TTL signals.
It can receive either single ended or differential input signals, selected by a switch. The outputs of these translators have 50 Ω back terminations, and, therefore, they can drive 50 Ω terminated or unterminated lines. These high speed translators facilitate testing of high speed digital communications circuits, where conversion of LVPECL clock and data signals to TTL level signals is often required.
The PRL-450LPD is designed to interface with Low-Voltage LVPECL circuits operating with a +3.3 V supply.
In the differential input mode, both inputs D and D of the PRL-450ND are terminated into 50 Ω/+1.3 V. In this mode, either one or both inputs can accept AC coupled signals as well.
In the single input mode, signals should be connected to the D inputs only. The D inputs are switched internally to VBB, nominally +2.0 V. The termination resistors, RT, for the D input channels are changed to 62 Ω.
Each unit is supplied with a ±8.5 V AC/DC Adapter and housed in an attractive 1.3 x 2.9 x 3.9-in. extruded aluminum enclosure.
(0° C ≤ TA ≤ 35° C)*
|VTT||D Input Termination Voltage (fixed)||1.18||1.30||1.43||V|
|VT1||D Input Termination Voltage||1.18||1.30||1.43||V|
|VT2||D Input Termination Voltage (variable)||1.8||2.0||2.2||V|
|VOL||Output Low Level||-150||0||300||mV|
|VOH||Output High Level||2.0||2.2||V|
|IDC1||DC Input Current, +8.5 V||430||mA|
|IDC2||DC Input Current, -8.5 V||-340||mA|
|VDC||DC Input Voltage||±7.5||±8.5||±12||V|
|VAC||AC/DC Adapter Input Voltage||103||115||127||V|
|tPLH||Propagation Delay to output ↑||2||ns|
|tPHL||Propagation Delay to output ↓||2||ns|
|tr/tf||Rise/Fall Times (10%-90%)||1.10||1.25||ns|
|tSKEW||Skew between any 2 outputs||200||500||ps|
|fmax||Max Clock Frequency||300||400||MHz|
|Size||1.3 x 2.9 x 3.9||in.|
|Weight, excluding AC adapter||7||Oz|
|Shipping weight, including AC adapter||4||lb.|