The PRL-4108UT is a series of 1:8 fanout differential line driver modules. All models have a floating 100 Ω universal differential input suitable for accepting LVDS, LVPECL, NECL, or RS422 signals.(1) They also have a logically ORed, 50 Ω TTL input with a minimum 1.0 V triggering threshold. Because the inputs are ORed a Hi level applied to either input can be used as a gate signal. Please see the block diagrams for more details.
The output is TTL, available either with dual SMA or dual BNC connectors per complementary output.
The PRL-4108UT high speed fanout line driver facilitates testing of high speed digital communications circuits and distribution of satellite or telemetry signals. The product suffix specifies the input and output connectors, e.g. BNC or SMA:
Additional connector and output logic options may be available upon special order.
The floating differential input accepts differential LVDS, LVPECL, NECL, RS422, or any 75 mV minimum differential signal within a common-mode range of -2.0 V to +3.0 V. When driven by LVPECL or NECL inputs, these signals must have internal 150 Ω or 200 Ω pull down resistors, respectively (known as a "source-biased" output). The PRL-4108UT differential input is compatible with all LVPECL or NECL output signals from the PRL family of products.
The TTL input has a selectable 50 Ω/1 kΩ input load and will trigger on a minimum 1.0 V threshold. The 1 kΩ is useful for interfacing with low-power circuits.
The eight pairs of complementary outputs are back-terminated and are designed for driving long lines. See the Specifications page for output levels.
The PRL-4108UT is supplied with a ±8.5 V/1.8 A AC/DC Adapter and housed in a 3.0 x 6.8 x 6.0-in. extruded aluminum enclosure. Available accessories include voltage distribution modules and mating cables.
Fig. 1A: PRL-4108UT Simplified Block Diagram
(0° C ≤ TA≤ 35° C)*
Unless otherwise specified, dynamic measurements are made with all rear-panel outputs terminated into floating 124 Ω, using 124 Ω shielded twisted pair Triax cables (Trompeter P/N PCGOW10PCG-36 or equivalent). Channel to channel skew and propagation delay measurements are made using a PRL-425NTR Differential Receiver with NECL outputs. Rise and fall time measurements are made using a Triax to SMA adapter and connecting the SMA outputs to a 50 Ω input scope.
|RT1-1||Differential Input Resistance||95||100||105||Ω|
|RINC||Common Mode Input Resistance||5||kΩ|
|RT2-1||Input Resistance, TTL 50 Ω||49||50||51||Ω|
|RT2-2||Input Resistance, TTL 1 kΩ||0.95||1.00||1.05||kΩ|
|VCMR||Input Common Mode Voltage||-2.0||3.0||V|
|VIH1||TTL Input Hi Level||1.0||5.0||V||Internally limited to 3.5V|
|VIL1||TTL Input Lo Level||-0.5||0.5||V|
|VOH1||Output High Level||2.2||2.5||2.6||V||RLOAD = 50 Ω|
|VOH2||Output High Level||4.4||5.0||5.2||V||RLOAD = 1 MΩ|
|VOL1||Output Low Level||-0.25||0.00||0.25||V|
|VAC1||AC Adapter Input Voltage, 120||108||115||127||V|
|VAC2||AC Adapter Input Voltage, 220||216||230||254||V|
|IDC1||DC Input Current, +8.5 V Supply||625||650||mA|
|IDC2||DC Input Current, -8.5 V Supply||-960||-1000||mA|
|tPROP1||Prop. Delay to Output ↑, Diff. Input||2.5||ns|
|tPROP2||Prop. Delay to Output ↑, TTL Input, 50 Ω||2.5||ns|
|tR||Rise Time (10%-90%)||1.4||2.0||ns||See Note 1|
|tF||Fall Time (10%-90%)||1.4||2.0||ns||See Note 1|
|tSKEW1||Ch./Ch. skew between any 2 True Outputs||250||500||ps|
|fMAX1||Max Clock Frequency, Diff. Input||150||175||MHz|
|fMAX2||Max Clock Frequency, TTL Input||100||125||MHz|
|Size||3.0”H x 6.8”W x 7.3”L||in||Including connectors|
|Weight||2||lbs||Excluding AC adapter|
|Shipping weight||6||lbs||Including AC adapter|
Please contact firstname.lastname@example.org for performance specifications on other models.