The PRL‑177A is a 2φ, TTL clock generator with two pairs of complementary 50 Ω back-terminated outputs. The internal VCO clock frequency fO is continuously variable over one octave, from less than 100 MHz to greater than 200 MHz, controlled by a 10-turn pot, for the 200 MHz model (PRL-177A-200; other VCO frequencies are also available). The VCO frequency can also be controlled over the same range using an external 0-16 V voltage source. The buffered VCO output fO is connected to two independent 2-bit dividers for generating the 2φ outputs. φ1 divides fO by 1, 2, 4 or 8, and provides output frequencies from less than 12.5 MHz to greater than 200 MHz. φ2 divides fO by 2, 4, 8 or 16, and provides output frequencies from less than 6.25 MHz to greater than 100 MHz. Except for the fO/1 outputs from φ1 (D0 = D1 = 00), all outputs are nearly perfect square waves, as they are derived from outputs of binary dividers. The duty cycle of the fO/1 output is typically better than 55%/45%.
The PRL‑177A‑200 is a Mini Modular Instrument (MMI) designed for everyday lab use. It is also a stable, low-jitter frequency source, covering the frequency range from less than 6.25 MHz to greater than 200 MHz. Its outputs (5 V/open circuit or 2.5 V/50 Ω) are ideally suited for testing CMOS/TTL circuits, amplifiers, discrete semiconductor devices, filters and other passive components, etc. The two sets of independent, complementary outputs are useful for split-cycle timing applications, sequential address simulation and for scope triggering or frequency monitoring using a counter. The PRL‑177A‑200 can also generate sine waves when used with a 7-pole low-pass Chebyshev filter built from a PRL Signal Conditioning Kit. The output waveforms are shown in Figs. 6 and 7, where 10 MHz and 5.2 MHz square waves are converted into sine waves (2.4 VPP) using the same filter. More information and links to filter calculators are available here.
With its clean, sub-ns rise-time and precision 50 Ω back-terminated outputs, the PRL‑177A‑200 is also an ideal TDR signal generator when used with the PRL‑812‑TDR passive splitter. This type of simple TDR generator is very affordable, and is well suited for testing cable impedance and for measuring biased input terminations that cannot be measured using a DVM. It can also replace expensive and cumbersome pulse generators, occupying less than 20 square inches of bench space, in applications where simple clock signals are needed. With the addition of a DC block, the PRL‑177A‑200 outputs can be converted into a ±1.25 V bipolar output for testing amplifiers.
The PRL‑177A‑200 is housed in a 1.3 x 2.9 x 5.1‑in. extruded aluminum enclosure and is supplied with a ±8.5 V, +17 V AC/DC Adapter.
(0° C ≤ TA ≤ 35° C)*
|IDC1||DC Input Current, +8.5 V*||+320||+335||mA|
|IDC2||DC Input Current, -8.5 V*||-410||-430||mA|
|IDC3||DC Input Current +17 V*||30||35||mA|
|VDC1||External DC Input Voltage 1||+7.5||+8.5||+12||V|
|VDC2||External DC Input Voltage 2||-12.0||-8.5||-7.5||V|
|VDC3||External DC Input Voltage 3||+19.0||+20.0||+22.0||V|
|VAC||AC Adapter Input Voltage||103||115||127||V|
|VOH1||Output Hi Level f ≤ 25 MHz||5||V||RL = 1 MΩ|
|VOH2||Output Hi Level 6.25 MHz ≤ f ≤ 200 MHz||2.4||2.5||V||RL = 50 Ω|
|VOL1||Output Lo Level f ≤ 25 MHz||-0.2||0||0.2||V||RL = 1 MΩ|
|VOL2||Output Lo Level 6.25 MHz ≤ f ≤ 200 MHz||-0.15||0||0.15||V||RL = 50 Ω|
|tR/tF||Rise/Fall Times (10%-90%), all outputs||750||850||ps||@ 100 MHz|
|DC1||Q1 Duty Cycle @ 100 MHz, D0 = D1 = 00||55||60||%|
|DC2||Duty Cycle, All Outputs, (D0 ≠ 0 || D1 ≠ 00)||50||%|
|VCO fMAX||Internal VCO maximum frequency||200||214||MHz||D0 = D1 = 00|
|VCO fMIN||Internal VCO minimum frequency||100||86||MHz||D0 = D1 = 00|
|fMAXφ1||φ1 Output maximum frequency||200||214||MHz||D0 = D1 = 00|
|fMIN φ1||φ1 Output minimum frequency||12.50||10.75||MHz||D0 = D1 = 11|
|fMAXφ2||φ2 Output maximum frequency||100||107||MHz||D2 = D3 = 00|
|fMIN φ2||φ2 Output minimum frequency||6.250||5.375||MHz||D2 = D3 = 11|
|tSKEW1||Skew ↔ Q1 and Q1||100||250||ps||f = 100 MHz|
|tSKEW2||Skew ↔ Q2 and Q2||100||250||ps||f = 100 MHz|
|tSKEW3||Skew ↔ Q1 and Q2||200||300||ps||f = 100 MHz|
|Δf||1 Hr. Frequency Stability, 23 °C ≤ TA ≤ 25 °C||0.1||%||1 hr warm up|
|JPPKPK||Period Jitter, peak to peak||20||40||ps|
|Enclosure Size||1.3 x 2.9 x 5.1||in.|
|Weight, excluding AC adapter||8||Oz|
|Shipping weight, including AC adapter||4||lb.|