The PRL-350TTL is a ready-to-use, high speed dual-channel comparator module. The The PRL-350TTL has a maximum clock frequency in excess of 300 MHz and has complementary TTL outputs designed for driving 50 Ω transmission lines with or without 50 Ω load terminations.
All models have DC coupled 50 Ω inputs and outputs. The input threshold voltage can be selected either from a set of preset values of +50 mV, 0 V or 50 mV using a common three-position switch. The input common mode range is -2.0 V to +3.0 V.
These high speed comparators are Mini Modular Instruments™ that can be used as peak detectors, threshold detectors, sine wave to square wave converters, window comparators or differential line receivers, etc. Typical minimum input voltage required at 300 MHz is 10 mVPP. into 50 Ω.
Each unit is supplied with a ±8.5 V AC/DC Adapter and housed in an attractive 1.3 x 2.9 x 3.9-in. extruded aluminum enclosure.
Fig. 1B PRL-350TTL Block Diagram
For the PRL-350TTL, very slight output waveform distortion and rise time degradation will occur when an unused complementary output is not terminated.
For optimum performance, however, all outputs should be terminated.
Anritsu Application Note for PON Module Testing with Anritsu MP1800A
Signal Quality Analyzer and PRL-350 Series Comparators (1.1 MB PDF)
BERT Level Translation
Anritsu engineers and customers around the world rely on our PRL-350 Series comparators for level conversion when testing Passive Optical Network (PON) modules.
PON module testing often requires converting the -1.0 to 0 V signals output by the MU181020A Pulse Pattern Generator cards to the LVTTL, PECL or LVPECL levels required by many ONU and OLT modules, typically for the Data, Pre-bias, and Reset signals.
Popular models include:
- PRL-350TTL, Dual Channel Comparator with TTL Outputs
- PRL-350LP, Dual Channel Comparator with LVPECL Outputs
- PRL-350P, Dual Channel Comparator with PECL Outputs
App Note and block diagram copyright and courtesy of Anritsu Corporation.
(0° C ≤ TA ≤ 35° C)*
Unless otherwise specified, dynamic measurements are made with all outputs terminated into 50 Ω/VTT, where VTT = -2 V for ECL outputs and 0 V for TTL outputs.
|VTH+||Preset positive threshold voltage||45||50||55||mV|
|VTH-||Preset negative threshold voltage||-55||-50||-45||mV|
|VTH0||Preset zero threshold voltage(1)||-2||0||2||mV|
|VOL||Output Low Level||-0.5||0||0.5||V|
|VOH||Output High Level||2.0||2.2||2.4||V|
|IDC1||DC Input Current, +8.5 V||300||325||mA|
|IDC2||DC Input Current, -8.5 V||-285||-300||mA|
|VDC||DC Input Voltage||±7.5||±8.5||±12||V|
|VAC||AC/DC Adapter Input Voltage||103||115||127||V|
|tPLH||Propagation Delay to output↑||2||ns|
|tPHL||Propagation Delay to output↓||2||ns|
|tSKEW||Skew between any 2 outputs||200||400||ps|
|Vin I||Minimum Input Voltage @ 150 MHz(3)||20||10||mVPP|
|Vin II||Minimum Input Voltage @ 250 MHz(3)||40||20||mVPP|
|VCM||Input Common Mode Range||-2.0||+3.0||V|
|fmax||Max. Clock Frequency||250||300||MHz|
|Size||1.3 x 2.9 x 3.9||in.|
|Weight, w/o AC adapter||7||Oz|
|Shipping weight, w/AC adapter||4||lb|
(1) If the switch is set to the center position (0 V threshold) a non-driven channel will oscillate and induce jitter in the driven channel. Connect any output to any input to stop the oscillation.
(2) 10%-90% for TTL.
For the PRL-350TTL, very slight output waveform distortion and rise time degradation will occur when an unused complementary output is not terminated. For optimum performance, however, all outputs should be terminated.
(3) In order to reduce jitter near fMAX, terminate the non-driven input into 50 Ω when the input voltage is less than 20 mVPP.