The PRL-426RS is an RS-422-to-LVDS Logic Level Translator.
The inputs of the PRL-422RS consist of two pairs of SMA connectors, each internally terminated with 124 Ω between the two signal pins. The SMA shields are tied to chassis ground. They are designed to interface with the 124 Ω differential Serial Data/Data or Clock/Clock outputs from data communications equipment. Model PRL-426RSTRI has Triax input connectors and SMA output connectors. Model PRL-426RSTR has SMA input connectors and Triax output connectors, and is available by special order.
The differential outputs are 50 Ω back-terminated and are designed for driving floating 100 Ω loads, normally the configuration used in LVDS input circuits. The output swing is typically 600 mV with a common mode voltage of 1.2 V. These high speed translators facilitate testing of high speed digital communications circuits where conversion of RS-422 clock and data signals to LVDS signals is often required.
Each unit is supplied with a ±8.5 V/1.8 A AC/DC Adaptor and housed in a 1.3 x 2.9 x 3.9-in. extruded aluminum enclosure. Available accessories include voltage distribution modules and brackets for mounting multiple units.
(0° C ≤ TA ≤ 35° C)*
|RINC||Common Mode Input Resistance||5k||Ω|
|VCM||Input Common Mode Voltage||-2.0||+3.0||V|
|VOL||Output Low Level||0.9||V|
|VOH||Output High Level||1.5||V|
|VCMV||Common mode voltage1||1.2||V|
|IDC1||DC Input Current, +8.5 VDC||85||100||mA|
|IDC2||DC Input Current, -8.5 VDC||-265||-300||mA|
|VDC||DC Input Voltage||±7.5||±8.5||±12||V|
|VAC||AC/DC Adapter Input Voltage||103||115||127||V|
|tPLH||Propagation Delay to output ↑||2||ns|
|tPHL||Propagation Delay to output ↓||2||ns|
|tR/tF||Rise/Fall Times (10%-90%)2||1.00||1.25||ns|
|tSKEW||Skew between any 2 outputs3||200||500||ps|
|fMAX||Max Clock Frequency4||500||625||MHz|
|Size||1.3 x 2.9 x 3.9||in.|
|Weight, excluding AC adapter||7||Oz|
|Weight, including AC adapter||4||lb.|