1:8 Differential Fanout Buffer System, NECL/TTL Input, NECL Outputs

SKU:

$ 9,832.50

Item	Description
88000102-4	Cable, triple voltage, with modular plugs, Length in ft.
88000103-4	Cable, triple voltage, with modular plug and pig tail leads, Length in ft.

Product Description
Diagrams
Applications
Specifications
Documents

Applications:

Converting TTL Inputs to Differential NECL Outputs
Long Line Driver/Level Translator
Reference Clock Distribution/Translation
1 PPS Distribution/IRIG-B Distribution
Telemetry and Avionics Distribution
Test and System Integration

Features:

1:8 Fanout with Complementary NECL Outputs
F_max > 1.5 GHz (NECL input)
Channel-to-channel Skew < 500 ps
t_R=300 ps Typ. with Output terminated into 50 Ω/-2V
Source-biased Outputs Drive Long Lines into 50 Ω/-2 V, AC-coupled 50 Ω loads, or floating differential 100 Ω loads
TTL and NECL Inputs (logically ORed)
NECL Input can be driven differentially, single-ended, or AC-coupled for sinewave conversion
Standard 19-in. Rack-Mount Chassis (2U) with optional slide rails

Description

The PRL-4534 is a low-skew, 1:8 differential fanout buffer system with 8 complementary NECL outputs and two inputs. The single-ended TTL input has a selectable 50 Ω or 1 KΩ to ground termination. The NECL input can be driven by single-ended NECL, differential NECL or AC-coupled sinewave signals. The TTL and NECL inputs are logically ORed; therefore a Hi level applied to either input can be used as a gate signal.

For the NECL input a toggle switch selects either single-ended or differential inputs. In the differential input mode both the NECL and NECL inputs and are terminated internally into 50 Ω/-2 V, and, therefore, either one or both inputs can accept AC-coupled signals as well.

In the single input mode, signal should be connected to the NECL input only. The NECL input is switched internally to VBB, nominally -1.3 V, and termination resistor R_T for the NECL input channel is changed to a Hi Z value. In the single-input mode, therefore, the NECL input should not be used for receiving signals. If the NECL inputs are not connected to an active signal, the switch should be in the Down position.

The input resistance of the TTL input can be selected to be either 50 Ω or 1 KΩ by a toggle switch. The 1 kΩ input is desirable when interfacing with low power circuits. The TTL input threshold voltage is 1.0 V minimum. When over-driven, the input voltage to the internal circuit is limited to 3.5 V through a current limiting 25 Ω series resistor. The output swing is typically 800 mV into 50 Ω/-2V or into an AC-coupled 50 Ω load.

All I/Os are DC coupled, with BNC inputs at the front of the unit and BNC outputs at the rear of the unit. The PRL-4534 is housed in a standard 19-in. rack-mountable enclosure with optional slide rails, powered by an autoswitching internal power supply suitable for 120/240 VAC, 50-60 Hz operation.

Models with a suffix, e.g. PRL-4534-C001, indicate a unit with a customer-specific silkscreen or labeling, but all PRL-4534 models are functionally equivalent.

(1) A related unit, the PRL-4533, has a universal differential input, and can accept LVDS, RS422, NECL, and LVPECL signals.

Fig. 1A: PRL-4534 Simplified Block Diagram

PRL-4534, Input Side

PRL-4534, Output Side

(0° C ≤ T_A≤ 35° C)*

Unless otherwise specified, dynamic measurements are made with all outputs terminated into 50 Ω/-2 V.

SYMBOL	PARAMETER	PRL-4534			UNIT	Comment
SYMBOL	PARAMETER	Min	Typ	Max	UNIT	Comment
R_T1-1	Input Resistance, NECL	49.5	50.0	50.5	Ω	Differential Input Mode
R_T2-1	Input Resistance, TTL 50 Ω	49	50	51	Ω
R_T2-2	Input Resistance, TTL 1 kΩ	0.95	1.00	1.05	kΩ
V_TT	D Input Termination Voltage	-2.20	-2.00	-1.80	V	NECL Input
V_T1	D Input Termination Voltage	-1.35	-1.30	-1.25	V	Single-ended mode
V_T2	D Input Termination Voltage	-2.20	-2.20	-1.80	V	Differential mode
V_IH1	TTL Input Hi Level	1.0		5.0	V	Internally limited to 3.5V
V_IL1	TTL Input Lo Level	-0.5		0.5	V
V_IH2	NECL Input Hi Level	-1.13	-0.90	-0.81	V
V_IL2	NECL Input Lo Level	-1.95	-1.60	-1.48	V
R_OUT	Output Resistance		7		Ω	Emitter of an NPN
V_OH	Output High Level	-1.13	-0.90	-0.81	V
V_OL	Output Low Level	-1.95	-1.60	-1.48	V
V_VA	AC Input Power		18	20	VA
V_AC	AC Input Voltage	108		254	V
t_PROP1	Prop. Delay to Output ↑, Diff. NECL Input		5.0		ns
t_PROP2	Prop. Delay to Output ↑, TTL Input, 50 Ω		5.5		ns
t_R	Rise Time (10%-90%)		220	300	ps	See Note 1
t_F	Fall Time (10%-90%)		220	300	ps	See Note 1
t_SKEW1	Ch./Ch. skew between any 2 True Outputs			500	ps
f_MAX1	Max Clock Frequency, NECL Input	1.5	1.7		GHz
f_MAX2	Max Clock Frequency, TTL Input	100	125		MHz
	Size	19.0”W x 3.5”H x 16.5”D			in	Excluding slide rails
	Weight	13			lbs

Notes:

1. Skew measurements valid when using same input logic level. TTL-input measurements made with TTL input set to 50 Ω. NECL-input measurements made with NECL input set for differential mode.

2. T_PROP and T_SKEW measurements made via PRL-8508 Test Mux, which provides 50 MHz input clocks in NECL and TTL logic as well as delay-matched NECL and TTL reference timing paths.