| Symbol | Parameter | Min | Typ | Max | Unit | Comments |
|---|
| Rin | External Clock Input Resistance | 49.5 | 50 | 50.5 | Ω | Except f input in single-ended mode |
| VTT | External Clock Input Termination Voltage | -2.2 | -2.0 0 | -1.8 | V | ECL input TTL input |
| IDC | DC Input Current | | +165/ -830 | +180/ -850 | mA | |
| VDC | DC Input Voltage | ±7.5 | ±8.5 | ±12 | V | |
| VAC | AC/DC Adapter Input Voltage | 103 | 115 | 127 | V | |
| VIH | External Clock Input Hi Level (Rin terminated to VTT) | -1.13 0.75 | -0.90 0.70 | -0.81 4.00 | V | NECL (VTT = -2 V) TTL (VTT= 0 V) |
| VIL | External Clock Input Lo Level (Rin terminated to VTT) | -1.95 -0.50 | -1.60 0.00 | -1.48 0.50 | V | NECL (VTT = -2 V) TTL (VTT= 0 V) |
| VOH | Output Hi Level @100 MHz (RL terminated to VTT) | -1.13 2.00 | -0.9 2.20 | -0.81
| V | NECL (VTT = -2 V) TTL (VTT= 0 V) |
| VOL | Output Lo Level @100 MHz (RL terminated to VTT) | -1.95 -0.50 | -1.60 0.00 | -1.48 0.50 | V | NECL (VTT = -2 V) TTL (VTT= 0 V) |
| tPLH1 | Propagation Delay to f output ↑ | | 2500 | | ps | From Ext Clk input |
| tPLH2 | Propagation Delay to NECL f/n output ↑ | | 3750 | | ps | From Ext Clk input |
| tPLH3 | Propagation Delay to TTL f/n output ↑ | | 2500 | | ps | From Ext Clk input |
| tr/tf1 | Rise/Fall Times (20%-80%), ECL outputs | | 600 | 700 | ps | Note (1) |
| tr/tf2 | Rise/Fall Times (10%-90%), TTL outputs | | 1100 | 1350 | ps | |
| tSKEW1 | Skew ↔ Φ1 NECL outputs | | 50 | 150 | ps | |
| tSKEW2 | Skew ↔ Φ1 TTL outputs | | 200 | 400 | ps | |
| tSKEW3 | Skew ↔ Φ1 NECL and TTL outputs | | 1300 | 1600 | ps | |
| tSKEW4 | Skew ↔ Φ1 and Φ2 NECL outputs | | 50 | 150 | ps | n≠1 |
| fMAX In | Max input clock frequency | 1000 | 1150 | 1500 | MHz | |
| fMAX Out | Max output frequency | 500 300 | 575 350 | | MHz | NECL outputs TTL outputs |
| | Size | 1.3 x 2.9 x 6.1 | in. | |
| | Weight | 10 | Oz | |