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PRL-260NT Programmable NECL/TTL Frequency Divider (Discontinued)

Basic Lab Tools > Frequency Dividers > PRL-260

The PRL-260NT has been replaced by the new PRL-260ANT. We are no longer taking orders for the PRL-260NT. Information contained on these pages is for information only.

Migration information:

  • The PRL-260ANT provides equivalent or superior functionality to the PRL-260NT except that it does not provide an undivided f output. The f output of the PRL-260NT has been replaced by the Φ2 output in the PRL-260ANT. If you require an undivided signal, a PRL-431N or PRL-414B fanout may be used to fan out your signal before it enters the PRL-260ANT.
  • The PRL-260ANT provides a higher typical fmax, higher maximum division ratios, lower channel-to-channel skew, lower TTL input threshold, and a second semi-independent Φ2 output. The PRL-260ANT is also 2" shorter in length.
  • Please contact support@pulseresearchlab.com for application migration support

Applications:

  • Systems clock simulation
  • Low-jitter NECL/TTL clock source
  • SONET clock generator
  • An Essential Lab Tool for Working with TTL/CMOS and ECL Circuits

Features:

  • f/2 to f/256, manually programmable, or square wave outputs to f/512
  • Single-ended NECL, differential NECL, or sinewave inputs with internal 50 Ω/VTT termination
  • f/n and f/n NECL Outputs with internal pull-down
  • Additional TTL Input and f, f NECL outputs
  • 20 ps typical Edge Jitter
  • 50 ps typical skew between f/n & f/n NECL outputs
  • 200 ps typical skew between f/n & f/n TTL outputs
  • 1.15 GHz typical maximum external clock input frequency 
  • Complementary NECL Outputs drive 50 Ω loads 
    terminated to VTT, AC-coupled or floating 50 Ω loads 
  • Complementary TTL Outputs drive long lines with or 
    without 50 Ω load terminations
  • DC coupled I/O's
  • Ready-to-Use module includes a ±8.5 V AC/DC Adapter

Description

The PRL-260NT is an 8-Bit, manually programmable frequency divider capable of running at input clock frequencies in excess of 1 GHz. A NECL input is logically OR-ed with a secondary TTL input. Complementary NECL and TTL f/n outputs are provided, as well as complementary NECL f/1 output. A signal applied to either the NECL or TTL input is divisible by any number between 2 and 256 using D1 through D8 of the DIP switch. D9 divides the f/n outputs further by 2 for f/2n square outputs. A logic Hi applied to either input disables the divider function.

The NECL input can accept either single-ended NECL, differential NECL, or sinewave signals, selectable by a switch, and has internal 50 Ω/ VTT terminations, where VTT is -2 V for NECL. The TTL input has a ground-referenced 50 Ω termination and the minimum signal required is only 1 V.

The NECL output is designed for driving 50 Ω loads terminated into VTT, and can also drive AC coupled or floating 50 Ω loads. The complementary 50 Ω back terminated TTL outputs can drive long 50 Ω lines with or without terminations.

Applications of the PRL-260 frequency divider includes precision clocks for high speed digital systems, low jitter clock source for testing A/D's, SONET clock generator, general purpose frequency division and Basic Lab Tool for working with NECL and TTL circuits. Each model is housed in a 1.3 x 2.9 x 8-in. extruded aluminum enclosure and is supplied with a ±8.5 V AC/DC adapter.

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Detail | DiagramSpecifications | Datasheet | DivisorTable.xls