Applications:
- System Clock Simulation
- Low Jitter NECL Clock Source
- SONET Clock Generator
- Laser Pump Synchronization
- Scope triggering
- PRBS/BERT synchronization
- Optimizing outputs from frequency synthesizers
- Testing high-speed serial/SERDES links (GB Ethernet, eSATA, PCIe,
HT, etc)
- An Essential Lab Tool for Working with ECL Circuits
Features:
- 2+ GHz typical maximum External Clock Input frequency
- f/1 - f/16 outputs with independent 2φ outputs
- φ1 output=f/1, 2, 4 or 8
- φ2 output=f/2, 4, 8 or 16
- Both φ1 and φ2 have two pairs of complementary NECL outputs
- Square wave outputs (except f/1)
- Internal 50 Ω/-2V Input Terminations also accept AC-coupled PECL or
sinewave signals
- 10 ps typical Edge Jitter
- 40 ps typical skew between f/n &
f/n NECL outputs (each phase)
- Complementary DC coupled NECL Outputs drive 50 Ω loads terminated to
-2V, AC coupled or floating 50 Ω loads
- SMA I/O Connectors
- Ready-to-Use 1.3 x 2.9 x 2.9-in. Module includes a ±8.5V AC/DC
Adapter
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Description:
The PRL-256N is an ECL input, manually programmable, two-phase
frequency divider with four pairs of complementary NECL outputs, capable
of running at input frequencies in excess of 2 GHz. The input selector
switch selects either single-ended or differential inputs. In the
differential input mode, both inputs CLK and
CLK are terminated
internally into 50 Ω/VTT, where VTT is equal to -2V
for NECL, and therefore, either one or both inputs can accept AC coupled
signals as well. In the single input mode, input signals should be
connected to the CLK input only. The
CLK input is internally
switched to VBB, nominally -1.3 V for NECL, and input resistor
RT for the
CLK input channel is
changed to 62 Ω.
The input buffer is followed by two banks of independent manually
programmable dividers, Φ1and Φ2. The input is divided by 1, 2, 4, or 8 for
the Φ1 bank via D0 and D1 of a two-bit DIP switch. It is divided by 2, 4,
8 or 16 for the Φ2 bank via D2 and D3 of a second two-bit DIP switch. Each
bank has two pairs of complementary outputs. All outputs are synchronous
with the input frequency and are square waves (50% duty cycle) except for
the f/1 outputs, which follow the input.
The outputs are suitable for driving long lines terminated into 50 Ω/-2
V or AC-coupled 50 Ω loads.
The PRL-256N is ideal for applications where a high-frequency divider
or pre-scalar is needed for triggering or down-sampling. The two phases of
output enable applications requiring two different ratios from a common
reference frequency, and the 1:2 fanout feature enables system
synchronization and monitoring/triggering applications from a single
reference clock source. Applications for the PRL-256N include data
acquisition, test, measurement, R&D, and system integration.
The unit includes an AC adapter for ready-to-use convenience on the
bench or in a system. All I/O connectors are SMA. The extruded aluminum
housing is suitable for mounting with the optional brackets.
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