PRL-255N/P NECL and PECL 3 GHz Frequency Dividers (÷2 and ÷4)

Basic Lab Tools > Frequency Dividers > PRL-255

Applications:

• GHz Frequency Division in Device Test and Systems Integration
• High speed Clock signal Generation for SONET applications
• An Essential Lab Tool for Working with GHz ECL Circuits

Features:

• 3 GHz Toggle Frequency
• Single-ended or Differential Inputs
• Internal 50 Ω/-2 V Input Terminations also accept Sine wave or AC coupled Signals from PECL
• Complementary Outputs drive 50 Ω Loads terminated to -2 V
• DC Coupled I/O’s Compatible with ECLinPS or 10 kH Devices
• SMA I/O Connectors
• Ready-to-Use 1.3 x 2.9 x 2.2-in. or 1.3 x 2.9 x 3.9-in.Module includes a ±8.5 V AC/DC Adapter

Description:

The PRL-255N and PRL-255P are, respectively, dual-channel NECL and PECL frequency divider modules, each containing ÷2 and a ÷4 frequency dividers capable of toggling at frequencies in excess of 3 GHz. 

The PRL-255CN is a dual-channel ÷2 and ÷4 frequency divider with DC-coupled, 50 Ω comparator inputs, and complementary NECL outputs. The maximum frequency of operation is greater than 2 GHz, and the minimum input signal required is 10 mV p-p at 300 MHz. It is ideally suited for dividing mV sinewave signals.

Any of these modules can also provide the ÷8 function by cascading the two dividers. The PRL-255N, PRL-255P, and PRL-255CN are essential lab tools for device test and systems integration in wireless and digital communications applications.

Each divider in the PRL-255N or PRL-255P has differential inputs and complementary outputs. A common switch selects either single-ended or differential inputs. In the differential input mode, both inputs CLK and CLK are terminated internally into 50 Ω/V_TT, and, therefore, either one or both inputs can accept AC coupled signals as well. In the single input mode, input signals should be connected to the CLK inputs only. The CLK inputs are internally switched to V_BB, and input resistors R_T's for the CLK input channels are changed to 62 Ω. Complementary outputs of both channels are designed for driving 50 Ω loads terminated into V_TT. With internal pull-down resistors, these outputs can also be AC coupled for driving 50 Ω loads terminated to ground or to other voltages, such as LVPECL circuits. Block diagrams of the PRL-255N and PRL-255P are shown in Fig. 1B.

The comparator input threshold voltage for the PRL-255CN can be set to +50 mV, 0 V or -50 mV using the common three-position switch provided. It can also be varied independently in each channel by applying a DC bias voltage to one of the two inputs. In this case, a feed through decoupling capacitor of 0.1 µf, such as the PRL-FTC-104, is recommended for preventing false triggering or oscillation if the bias voltage contains varying components, such as noise. Input common mode range is -2.5 V to +4 V. To prevent oscillation in a non-driven channel when the preset threshold is set to 0 V, connect an output to an input so that the two inputs are not at the same voltage. 

The PRL-255N and PRL-255P are housed in a 1.3 x 2.9 x 2.2-in. extruded aluminum enclosure, and the PRL-255CN is housed in a 1.3 x 2.9 x 3.9-in. enclosure. Each modules is supplied with a ±8.5 V/1.4 A AC/DC Adapter.

***All prices are for domestic orders only. For international orders, please add 15%. Prices are subject to change without notice. Please consult factory for additional information at 310-515-5330.***

Detail | Diagram | Specifications | PRL-255N/255P Datasheet | PRL-255CN Datasheet