A1: ECL stands for Emitter Coupled Logic. The basic circuit configuration consists of a pair of NPN transistors with their emitters connected together and fed by a current source as show in Fig. 1. 

Q₁ and Q₂ are normally referred to as the differential switch. In the steady state, either Q₁ or Q₂ is on but not both, and the output logic state is determined by the voltage difference between the bases of Q₁ and Q₂. If V_b1 – V_b2 > 200 mV, Q₁ will be turned on and Q₂ turned off, and vice versa.

The inputs can be driven either differentially or single-ended. In the single-ended mode, the non-driven base must be connected to a suitable bias voltage, V_BB, which is either supplied internally by the device, or externally. The voltages developed at the collectors of Q₁ and Q₂ are connected to a pair of emitter followers, Q₃ and Q₄. The outputs are taken at the emitters of Q₃ and Q₄. Note that the output emitters are open, and, unlike TTL/CMOS circuits, there will be no output until a pull-down resistor is connected to the open emitter. This pull-down resistor plays a very important role in determining the performance of the ECL circuit, (see other FAQs). A more detailed description of the basic ECL circuits and the variation of circuit configurations can be found in the Motorola MECL Data book and the newer High Performance ECL Data book.

For a listing of PRL products using ECL Circuits, click here

A2: There are normally two supply voltages specified. The more positive supply voltage is labeled V_CC and the more negative supply voltage V_EE. Usually, only one supply voltage is used, and the other is ground. One may also see ECL evaluation boards with both positive and negative voltages used in order to simplify interfacing with ground-referenced instruments.

In the newer ECLinPS and ECLinPS Lite families of GHz ECL devices, both 10 K and 100 K devices can share the same supply voltages of V_CC-V_EE = -5.2 V. The industrial standard for ECL supply voltages are V_CC=0 V, and V_EE = -5.2 V.

For a listing of PRL products using ECL Circuits, click here

A3: LVECL devices are ECL devices designed for use with V_EE = -3.3 V. They are I/O compatible with standard ECL devices.

The "P" in PECL stands for positive. PECL Circuits are generally identical to ECL circuits, except the V_CC supply is 5 V and the V_EE supply is ground. There are special PECL devices that are designed strictly for +5 V supply only.

LVPECL Circuits are PECL circuits designed for use with V_CC = 3 V or 3.3 V, the same supply voltage as for Low Voltage CMOS devices. As one can see, the PECL and LVPECL devices are designed to be supply voltage compatible with TTL/CMOS and LVCMOS circuits, respectively.

For a listing of PRL products using ECL Circuits:    click here

A4: For the sake of simplicity, only nominal values will be used for the discussion here. Worst case values as a function of loading, temperature and supply voltage variations can be found in the Motorola Data Book.

For standard ECL circuits, the Hi and Lo logic levels are defined to be V_CC-0.8 V and V_CC-1.6 V, respectively. Since these levels are referenced to the V_CC supply only, they are applicable to ECL’s, LVECL’s, PECL’s and LVPECL’s. The following table lists the nominal numerical values of logic levels for these circuits, including the internal bias voltage V_BB and the external termination voltage V_TT, which must be supplied by the user.

When driving these devices using a 50 Ω-output generator, the output Hi and Lo levels of the generator must be set so that the correct levels are produced at the input of these devices. For a device with input terminated to 50 Ω/V_TT, the resistor divider effect between the generator source resistance and the load must be taken into account, and the equivalent circuit is shown in Fig. 5. 

From Fig. 5, the required open circuit Hi and Lo levels from the 50 Ω-output generator are easily calculated and are listed below as V_OHPG and V_OLPG.

Table I: I/O and Bias voltage levels for ECL, LVECL, PECL and LVPECL devices

It is important to note that the I/O levels, V_BB and V_TT for both ECL and LVECL are the same but not so for PECL and LVPECL devices. It should be pointed out that these logic levels are affected some what by the loading conditions. For ECL’s, for example, under heavy loading conditions, V_OH may be –0.95 V instead of –0.8 V. Similarly, V_OL may be –1.75 V instead of –1.6 V. For convenience sake, the V_OLPG values can be chosen to be the same as the V_TT values, resulting, in slightly different propagation delays between the output rising and falling edges, because the input waveform is no longer symmetrical with respect to V_BB.

PRL products using ECL Circuits:

Our line of Logic Level Translators

The following Basic Lab Tools

• PRL-170 ECL Xtal Clock Source
• PRL-255 ECL Frequency Divider
• PRL-258 4 Phase ECL Clock Generator
• PRL-430 Dual Channel Differential ECL Receiver
• PRL-431 1:2 Differential Fan Out ECL Buffer
• PRL-434 1:4 Differential Fan Out ECL Buffer
• PRL-435 Differential Input AND Gate
• PRL-470 High Speed, Line Driver-Level Translator
• PRL-480 Dual Channel Programmable ECL Delay Module